Semiconductor devices such as Integrated Circuits (IC's), System-On-a-Chip (SOC), or other chips often have millions of transistors. These devices are often designed at a higher level using Register-Transfer-Level (RTL) descriptions that specify logical operation of the chip but do not specify transistors or logic gates. Computer-Aided-Design (CAD) software and tools allow designers to specify chip operation at a higher level, increasing efficiency and time-to-market. CAD software later creates the gates, transistors, and wiring needed to implement the logical behavior specified in the RTL. However, the timing of various signals within the chip can vary greatly depending on the layout, transistor sizes, and wire lengths chosen by the software.
Semiconductor devices are specified (spec'ed) to operate within certain parameters, such as a maximum power draw and a maximum clock frequency. While semiconductor manufacturing processes are very precise, process variations do occur. Although the manufacturing process may target a typical device, sometimes process variations produce slower chips or faster chips. As device sizes shrink, larger relative variations may occur.
Chips may be tested to determine their power draw and speed, and these chips may be sorted into slow-chip bins, fast-chip bins, and typical-chip bins. The faster chips may be sold as faster speed grades, while the slower chips may be sold for slower speed grades. Unfortunately, such process skews are not always reproducible or planned but may occur randomly, making for logistical difficulties. Therefore all process skews are often lumped together. The slowest expected process skews determine the specified speed of the device, while the fastest expected process skews determine the specified maximum power dissipation.
FIG. 1 is a graph showing how process variations affect device specifications. The slowest process skew (SS) has the lowest power and the lowest performance or speed. A typical process (TT) has a better power and performance product. The fastest process skew (FF) has the highest performance and speed, but also consumes the most power.
All three process skews—slow, typical, and fast, share the same device specifications when no grade sorting is performed. Devices produced with the slowest process determine the speed specs such as the maximum clock frequency, or the minimum clock-to-output delay times. However, the fast devices consume more power than do the slower devices, so power specs are determined by devices manufactured by the fast process skews. The power-supply voltage VDD is usually fixed.
The performance and power specs are determined by the worst-case devices over the expected process skews. Slow devices set the speed specs and fast devices set the power specs. This is not optimal, since fast devices are spec'ed slower than they can actually operate, and slow devices actually draw less power than spec'ed.
Specialized sensors may be added to chips to facilitate at-speed testing. Dummy bit lines have been added to RAM arrays to adjust bit-line sensing circuits. An oscillator or a canary circuit may be added to track process variations. However, the actual circuit may be much more complex than an oscillator, resulting in tracking errors. For logic chips, a dummy path and an on-chip timing sensor may be added. The timing sensor can report its results to a tester or even to an on-chip controller that can adjust operating conditions, such as to slow down or stop a clock to reduce power consumption.
The actual critical paths in a logic circuit are the first to fail as the applied clock speed is increased. The actual critical path will have different characteristics than a dummy load to a sensor. Cross talk from neighboring nodes will differ even if gates, capacitances, and wiring traces are exactly mimicked. Extensive corner analysis may be needed to set sufficiently large margins to account for the differences between dummy paths and actual critical paths.
While such on-chip dummy paths and sensors are useful, it is desired to measure the actual critical paths rather than measure a dummy path. It is desired to add a timing sensor to an actual critical path on a chip so that the timing sensor is measuring the delay of the same physical path that carries functional data during operation of the chip. It is desired to have CAD software that automatically selects which paths to add sensors to.
It is desired to adjust or scale the internal power-supply voltage VDD to account for measured process variations. It is desired to add a timing sensor to an actual critical path on a chip so that the timing sensor is measuring the delay of the same physical path that carries functional data during operation of the chip. It is desirable to use the same gates, wires, and loads of a functional critical path. It is desired to have software that automatically selects which paths within the circuit to add sensors to. It is desired to select paths that are the slowest paths, but also to select paths that would operate without timing hazards that could disrupt sensor accuracy. It is desired to have CAD software select critical paths and add and connect sensors and a VDD controller that can adjust the circuit's internal power-supply voltage to compensate for measured conditions.